Phase locked loop circuit and method of locking a phase

ABSTRACT

A phase locked loop circuit and method of locking a phase. The phased locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ≧4) internal clock signals. The phased locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals.

PRIORITY STATEMENT

This U.S. non-provisional application claims priority under 35 U.S.C.§119 to Korean Patent Application No. 2005-0053652, filed on Jun. 21,2005, the entire contents of which are incorporated by reference.

BACKGROUND OF THE INVENTION

FIG. 1A illustrates a conventional phase locked loop, which may includea phase frequency detector (PFD) 10, a charge pump (CP) 12, a loopfilter (LF) 14, a voltage controlled oscillator (VCO) 16, one or moredividers 18-1, 18-2, and/or one or more dividers 20.

The phase frequency detector (PFD) 10 may receive an external clocksignal ECLK and generate an UP or DN signal in response to a phasedifference between the external clock signal ECLK and a feedback clocksignal DCLK. When the phase of the external input signal ECLK leads thatof the feedback clock signal DCLK, the UP signal is activated. When thephase of ECLK lags that of DCLK, the DN signal is activated.

The charge pump (CP) 12 and/or the loop filter (LF) 14 may increase thelevel of a control voltage (Vc), in response to the activated UP signaland may decrease the level of the control voltage Vc, in response to theactivated DN signal.

For example, when the frequency of ECLK is 1 GHz, in order to acquireone or more final internal clocks of 2 GHz frequency, a conventionalvoltage controlled oscillator (VCO) 16 may generate two clock signalsCLK and CLKB, each with a frequency of 4 GHz. The divider 18-1 maydivide the clock signal CLK to generate two clock signals ICLK0,ICLK180, each with a frequency of 2 GHz. The divider 18-2 may divide theinverted clock signal CLKB to generate two clock signals ICLK90,ICLK270, each with a frequency of 2 GHz.

The divider 20 may receive one of the clock signals ICLK0, ICLK180,ICLK90 and ICLK270 and output the divided clock signal DCLK, with afrequency of 1 GHz, which equals the frequency of ECLK.

That is, in order to acquire final internal clock signals ICLK0,ICLK180, ICLK90 and ICLK270 having a higher frequency than that of ECLK,the divider 20 is necessary. In other words, when a PLL does not includethe divider 20, the frequencies of the final internal clocksICLK0˜ICLK270 are equal to the frequency of external input clock ECLK.However, the frequency of each of CLK and CLKB must be four times higherthan that of ECLK to generate final internal clocks ICLK0˜ICLK270, witha frequency twice that of ECLK.

As a result, a problem with conventional phase locked loops is thathigher frequency internal clock signals (for example, 4 GHz or higher)may be difficult to generate from a VCO when a power voltage (VCC) islow (for example, less than 2VDD or under 1.8V). Further, conventionalphase locked loops may have a larger chip area as a result of the numberof dividers.

FIG. 1B illustrates another conventional phase locked loop. Theconventional phase locked loop of FIG. 1B includes some of the sameelements as that of FIG. 1A. In addition to one or more dividers 18-1,18-2, and one or more dividers 20, the conventional phase locked loop ofFIG. 1B may further include one or more dividers 18-3, 184, 18-5, and18-6. As shown, the frequency of each of CLK and CLKB is eight timeshigher than that of ECLK while the frequency of each of iCLK0˜iCLK270 isfour times higher than that of ECLK. Further, the frequency of each ofICLK0˜ICLK315 is two times higher than that of ECLK.

As an example, if the frequency of ECLK is 1 GHz, the frequency of CLKand CLKB is 8 GHz, the frequency of iCLK0˜iCLK270 is 4 GHz, and thefrequency of ICLK0˜ICLK315 is 2 GHz. Under low power supply voltageconditions (for example, less than 2VDD), a conventional VCO 16 cannotgenerate the output clocks CLK and CLKB with a frequency of 8 GHz.

FIG. 2 illustrates a conventional voltage controlled oscillator, forexample, VCO 16 of FIGS. 1A or 1B. The conventional voltage controlledoscillator may include a first ring oscillator 16-1 including one ormore inverters I1, I2, I3, formed in a loop configuration, a second ringoscillator 16-2 including one or more inverters I4, I5, I6, formed in aloop configuration (for example, the same configuration as the firstring oscillator 16-1) and a latch circuit 16-3 including one or moreinverters I7, I8, for latching CLK and CLKB.

The frequency of the output clock CLK/CLKB may be controlled in responseof the level of Vc. When the level of Vc is increased, the frequency ofthe output clock CLK/CLKB may be increased. When the level of Vc isdecreased, the frequency of the output clock CLK/CLKB may be decreased.A problem may be that the Vc is at too low a level (if supplied by a lowpower supply) so that high frequency output clock signals CLK/CLKB (forexample, 4 GHz or more) can not be generated.

FIG. 3A is a timing diagram illustrating example operation of aconventional phase locked loop, for example, the conventional phaselocked loop of FIG. 1A.

The voltage controlled oscillator 16 may generate two clock signals CLKand CLKB, having a phase difference of 180°, and which have a frequencyfour times higher frequency than that of ECLK. The frequency of each ofICLK0˜ICLK270 may be two times higher than that of ECLK.

FIG. 3A illustrates that an internal clock ICLK0 is locked with theexternal clock ECLK. When a power supply voltage is a higher level, allof the above internal clock signals may be generated normally. However,when a power supply voltage is a lower level, it is impossible togenerate the timing diagram of FIG. 3A.

FIG. 3B is a timing diagram illustrating example operation of aconventional phase locked loop, for example, the conventional phaselocked loop of FIG. 1B.

The voltage controlled oscillator 16 may generate two clock signals CLKand CLKB having a phase difference of 180°, and which have a frequencyeight times higher than that of ECLK. The frequency of each ofiCLK0˜iCLK270 may be four times higher than that of ECLK. The frequencyof each of ICLK0˜ICLK315 may be two times higher than that of ECLK.

FIG. 3B illustrates that an internal clock ICLK0 is locked with theexternal clock ECLK. When a power supply voltage is a higher level, allof the above internal clock signals may be generated normally. However,as set forth above, when a power supply voltage is a lower level, it isimpossible to generate the timing diagram of FIG. 3B.

SUMMARY OF THE INVENTION

Example embodiments of the present invention are directed to phaselocked loop circuits and methods of locking the phase of a signal.

Example embodiments of the present invention are directed to phaselocked loop circuits and methods of locking the phase of a feedbackclock signal to an external clock signal.

Example embodiments of the present invention are directed to memorydevices and methods of writing data to and reading data from a memorycell array.

Example embodiments of the present invention are directed to memorysystems and methods of writing data to and reading data from a memory,including a plurality of memory devices.

Example embodiments of the present invention are directed to phaselocked loop circuits and methods of locking the phase of a feedbackclock signal to an external clock signal, which directly generate atleast n (where n is an integer ≧4) internal clock signals.

Example embodiments of the present invention are directed to memorydevices and methods of writing data to and reading data from a memorycell array, which directly generate at least n (where n is an integer≧4) internal clock signals.

Example embodiments of the present invention are directed to memorysystems and methods of writing data to and reading data from a memory,including a plurality of memory devices, which directly generate atleast n (where n is an integer ≧4) internal clock signals.

Example embodiments of the present invention are directed to phaselocked loop circuits and methods of locking the phase of a feedbackclock signal to an external clock signal, which include at least fourloops and generate multiple internal clock signals.

Example embodiments of the present invention are directed to memorydevices and methods of writing data to and reading data from a memorycell array, which include at least four loops and generate multipleinternal clock signals.

Example embodiments of the present invention are directed to memorysystems and methods of writing data to and reading data from a memory,including a plurality of memory devices, which include at least fourloops and generate multiple internal clock signals.

Example embodiments of the present invention are directed to phaselocked loop circuits, memory devices, and memory systems, which includea voltage controlled oscillator circuit including a hyper ringoscillator.

Example embodiments of the present invention are directed to phaselocked loop circuits, memory devices, and memory systems, in which avoltage controlled oscillator circuit includes one or more loopcircuits.

Example embodiments of the present invention are directed to phaselocked loop circuits, memory devices, and memory systems, which includea reduced number or no dividers.

Example embodiments of the present invention are directed to phaselocked loop circuits, memory devices, and memory systems, which have areduce chip areas because fewer dividers or no dividers are needed.

Example embodiments of the present invention are directed to phaselocked loop circuits, methods of locking the phase of a feedback clocksignal to an external clock signal, memory devices, methods of writingdata to and reading data from a memory cell array, memory systems, andmethods of writing data to and reading data from a memory, including aplurality of memory devices which may generate higher frequency internalclock signals (for example, 2 GHz or more) even though a power supplyvoltage VDD is relatively low (for example, less than 2V).

In an example embodiment of the present invention, a phase locked loopcircuit may include a phase detector receiving an external clock signaland a feedback clock signal and outputting an up signal when a phase ofthe external clock signal leads a phase of the feedback clock signal andoutputting a down signal when the phase of the external clock signallags the phase of the feedback clock signal, a loop filter circuitincreasing a control voltage in response to the up signal and decreasingthe control voltage in response to the down signal, and a voltagecontrolled oscillator circuit receiving the control voltage and directlygenerating at least n (where n is an integer ≧4) internal clock signals.

In another example embodiment of the present invention, the voltagecontrolled oscillator circuit includes a hyper ring oscillator.

In another example embodiment of the present invention, the loop filtercircuit is a low pass filter.

In another example embodiment of the present invention, the loop filtercircuit is a digital loop filter circuit.

In another example embodiment of the present invention, the loop filtercircuit is an analog loop filter circuit.

In another example embodiment of the present invention, the voltagecontrolled oscillator circuit does not include a divider.

In an example embodiment of the present invention, a method of lockingthe phase of a feedback clock signal to an external clock signalincludes receiving the external clock signal and the feedback clocksignal, outputting an up signal when a phase of the external clocksignal leads a phase of the feedback clock signal and outputting a downsignal when the phase of the external clock signal lags the phase of thefeedback clock signal, increasing a control voltage in response to theup signal and decreasing the control voltage in response to the downsignal, and directly generating at least n (where n is an integer ≧4)internal clock signals, and generating the feedback clock signal from atleast one of the n internal clock signals.

In an example embodiment of the present invention, a phase locked loopcircuit includes a phase detector receiving an external clock signal anda feedback clock signal and outputting an up signal when a phase of theexternal clock signal leads a phase of the feedback clock signal andoutputting a down signal when the phase of the external clock signallags the phase of the feedback clock signal, a loop filter circuitincreasing a control voltage in response to the up signal and decreasingthe control voltage in response to the down signal, and a voltagecontrolled oscillator circuit, including at least four loops, receivingthe control voltage and generating multiple internal clock signals.

In an example embodiment of the present invention, a method of lockingthe phase of a feedback clock signal to an external clock signalincludes receiving the external clock signal and the feedback clocksignal, outputting an up signal when a phase of the external clocksignal leads a phase of the feedback clock signal and outputting a downsignal when the phase of the external clock signal lags the phase of thefeedback clock signal, increasing a control voltage in response to theup signal and decreasing the control voltage in response to the downsignal, and generating at least n (where n is an integer ≧4) internalclock signals, each from a separate loop.

In an example embodiment of the present invention, a memory deviceincludes a memory cell array, a phase locked loop circuit receiving anexternal clock signal and a feedback clock signal and directlygenerating at least n (where n is an integer ≧4) internal clock signals,a control signal generator circuit for receiving the at least n internalclock signals and generating p control signals (where p is an integer≧3), at least one serial to parallel converter, for receiving a serialbit stream bits and converting the serial bit stream into a parallel bitstream that can be written to the memory cell array, in response to eachof the p control signals, and at least one parallel to serial converter,for receiving a parallel bit stream from the memory cell array andconverting the parallel bit stream into a serial bit stream, in responseto each of the p control signals.

In an example embodiment of the present invention, a method of writingdata to and reading data from a memory cell array includes receiving anexternal clock signal and a feedback clock signal, directly generatingat least n (where n is an integer ≧4) internal clock signals in responseto the external clock signal and the feedback clock signal, generating pcontrol signals (where p is an integer ≧3) in response to the at least ninternal clock signals, receiving a serial bit stream and converting theserial bit stream into a parallel bit stream that can be written to thememory cell array, in response to each of the p control signals, andreceiving a parallel bit stream from the memory cell array andconverting the parallel bit stream into a serial bit stream, in responseto each of the p control signals.

In an example embodiment of the present invention, a memory systemincludes a memory including a plurality of memory devices, each memorydevice including a memory cell array, each memory device including aphase locked loop circuit receiving an external clock signal and afeedback clock signal and directly generating at least n (where n is aninteger ≧4) internal clock signals, a control signal generator circuitfor receiving the at least n internal clock signals and generating pcontrol signals (where p is an integer ≧3), at least one serial toparallel converter, for receiving a serial bit stream of m (where m isan integer ≧1) bits and converting the serial bit stream of m bits intoa parallel bit stream that can be written to the memory cell array, inresponse to each of the p control signals, and at least one parallel toserial converter, for receiving a parallel bit stream from the memorycell array and converting the parallel bit stream into a serial bitstream, in response to each of the p control signals and a memorycontroller supplying the external clock signal to the phased locked loopof each of the plurality of memory devices so each of the phased lockedloops may generate the at least n internal clock signals provided to thecontrol signal generator circuit and supplying a command signal and anaddress signal to read the parallel bit stream from any of the pluralityof memory devices and write the serial bit stream to any of theplurality of memory devices.

In an example embodiment of the present invention, a method of writingdata to and reading data from a memory, including a plurality of memorydevices includes supplying an external clock signal to each of theplurality of memory devices, directly generating at least n (where n isan integer ≧4) internal clock signals from the external clock signal,generating p control signals (where p is an integer ≧3) in response tothe at least n internal clock signals, receiving a serial bit stream andconverting the serial bit stream into a parallel bit stream that can bewritten to any of the plurality of memory devices, in response to eachof the p control signals, supplying a write command signal and anaddress signal to write the parallel bit stream to at least one of theplurality of memory devices, supplying a read command signal and anaddress signal to read a parallel bit stream from at least one of theplurality of memory devices, and receiving the parallel bit stream fromany of the plurality of memory devices and converting the parallel bitstream into a serial bit stream, in response to each of the p controlsignals.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description of example embodiments provided below and theaccompanying drawings, which are given for purposes of illustrationonly, and thus do not limit the invention.

FIG. 1A illustrates a conventional phase locked loop.

FIG. 1B illustrates another conventional phase locked loop.

FIG. 2 illustrates a conventional voltage controlled oscillator.

FIG. 3A is a timing diagram illustrating example operation of aconventional phase locked loop.

FIG. 3B is a timing diagram illustrating example operation of anotherconventional phase locked loop.

FIG. 4 illustrates a phase locked loop in accordance with an exampleembodiment of the present invention.

FIG. 5A illustrates a voltage controlled oscillator in accordance withan example embodiment of the present invention.

FIG. 5B is an example equivalent diagram of the voltage controlledoscillator of FIG. 5A.

FIG. 6A illustrates a voltage controlled oscillator in accordance withanother example embodiment of the present invention.

FIG. 6B is another illustration of the voltage controlled oscillator ofFIG. 6A.

FIG. 6C is an example equivalent diagram of the voltage controlledoscillator of FIG. 6A.

FIG. 7 is a timing diagram illustrating operation of the phase lockedloop of FIG. 6A in accordance with an example embodiment of the presentinvention.

FIG. 8A illustrates a voltage controlled oscillator in accordance withanother example embodiment of the present invention.

FIG. 8B is an example equivalent diagram of the voltage controlledoscillator of FIG. 8A.

FIG. 9 is a timing diagram illustrating operation of the voltagecontrolled oscillator of FIG. 8A in accordance with an exampleembodiment of the present invention.

FIG. 10 is an example equivalent diagram of a voltage controlledoscillator in accordance with another example embodiment of the presentinvention.

FIG. 11 is a timing diagram illustrating operation of the voltagecontrolled oscillator of FIG. 10 in accordance with an exampleembodiment of the present invention.

FIG. 12 is an example equivalent diagram of a voltage controlledoscillator in accordance with another example embodiment of the presentinvention.

FIG. 13 is a timing diagram illustrating operation of the voltagecontrolled oscillator of FIG. 12 in accordance with an exampleembodiment of the present invention.

FIG. 14A illustrates a phase detector in accordance with an exampleembodiment of the present invention.

FIG. 14B illustrates a phase detector in accordance with another exampleembodiment of the present invention.

FIG. 14C is a timing diagram illustrating operation of the phasedetector of FIG. 14B in accordance with an example embodiment of thepresent invention.

FIG. 15A illustrates a charge pump and a loop filter in accordance withan example embodiment of the present invention.

FIG. 15B is a timing diagram illustrating operation of the charge pumpand a loop filter of FIG. 15A in accordance with an example embodimentof the present invention.

FIG. 15C is a timing diagram illustrating operation of the charge pumpand a loop filter of FIG. 15A in accordance with another exampleembodiment of the present invention.

FIG. 16A illustrates a divider in accordance with an example embodimentof the present invention.

FIG. 16B illustrates a divider in accordance with another exampleembodiment of the present invention.

FIG. 17 illustrates a phase locked loop in accordance with anotherexample embodiment of the present invention.

FIG. 18 illustrates a phase locked loop in accordance with anotherexample embodiment of the present invention.

FIG. 19 illustrates a digital-to-analog converter and a loop filter inaccordance with an example embodiment of the present invention.

FIG. 20 illustrates a simulation of frequency variation of a voltagecontrolled oscillator in accordance with an example embodiment of thepresent invention compared to frequency variation of a conventionalvoltage controlled oscillator.

FIG. 21 illustrates a memory system including a phase locked loop inaccordance with an example embodiment of the present invention.

FIG. 22 illustrates a memory device including a phase locked loop inaccordance with an example embodiment of the present invention.

It should be noted that these Figures are intended to illustrate thegeneral characteristics of methods and devices of example embodiments ofthis invention, for the purpose of the description of such exampleembodiments herein. These drawings are not, however, to scale and maynot precisely reflect the characteristics of any example embodiment, andshould not be interpreted as defining or limiting the range of values orproperties of example embodiments within the scope of this invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments of the present invention will now bedescribed more fully with reference to the accompanying drawings inwhich some example embodiments of the invention are shown.

Detailed illustrative embodiments of the present invention are disclosedherein. However, specific structural and functional details disclosedherein are merely representative for purposes of describing exampleembodiments of the present invention. This invention may, however, beembodied in many alternate forms and should not be construed as limitedto only the embodiments set forth herein.

Accordingly, while example embodiments of the invention are capable ofvarious modifications and alternative forms, embodiments thereof areshown by way of example in the drawings and will herein be described indetail. It should be understood, however, that there is no intent tolimit example embodiments of the invention to the particular formsdisclosed, but on the contrary, example embodiments of the invention areto cover all modifications, equivalents, and alternatives falling withinthe scope of the invention. Like numbers refer to like elementsthroughout the description of the figures.

It will be understood that, although the terms first, second, etc. ornumbers 1, 2, etc. may be used herein to describe various elements,these elements should not be limited by these terms. These terms areonly used to distinguish one element from another. For example, a firstelement could be termed a second element, and, similarly, a secondelement could be termed a first element, without departing from thescope of example embodiments of the present invention. As used herein,the term “and/or” includes any and all combinations of one or more ofthe associated listed items.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between” versus “directly between”, “adjacent” versus “directlyadjacent”, etc.).

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments of the invention. As used herein, the singular forms “a”,“an” and “the” are intended to include the plural forms as well, unlessthe context clearly indicates otherwise. It will be further understoodthat the terms “comprises”, “comprising,”, “includes” and/or“including”, when used herein, specify the presence of stated features,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,integers, steps, operations, elements, components, and/or groupsthereof.

It should also be noted that in some alternative implementations, thefunctions/acts noted may occur out of the order noted in thedescription. For example, two functions/acts described in succession mayin fact be executed substantially concurrently or may sometimes beexecuted in the reverse order, depending upon the functionality/actsinvolved.

FIG. 4 illustrates a phase locked loop in accordance with an exampleembodiment of the present invention, which may include a phase frequencydetector (PFD) 10, a charge pump (CP) 12, a loop filter (LF) 14, avoltage controlled oscillator (VCO) 16′, and/or one or more dividers 20.The VCO 16′ may directly generate a plurality of higher frequencyinternal clock signals ICLK1˜ICLKn (for example, 2 GHz or more)corresponding to internal clock signals ICLK0˜ICLK270 of FIG. 1A eventhough a power supply voltage VDD is relatively low (for example, lessthan 2V). In an example embodiment, the VCO 16′ may be implemented witha hyper ring oscillator, which may generate directly a plurality ofinternal clock signals (for example, four clock signals or more) whichhave a regular phase difference. In addition, a VCO in accordance withan example embodiment of the present invention, for example VCO 16′, mayhave a reduced chip area because dividers, for example, dividers 18-1,18-2, and/or 20 are not needed.

FIG. 5A illustrates a voltage controlled oscillator in accordance withan example embodiment of the present invention, which includes aplurality of inverters I1 to I6. In an example embodiment, a first loopcircuit includes inverters I4, I5, I2 and I3, a second loop circuitincludes inverters I1, I2 and I3, and a third loop circuit includesinverters I4, I6 and I3. Clock ICLK0 may be generated by a phasecombination of clock signals generated from I1 and I5. Each clock signalICLK90, ICLK180, ICLK270 may similarly be generated by a principle, suchas phase combination. In an example embodiment, the phase of node D maylead the phase of node A by 90°. The phase of node C may lead the phaseof node D by 90°. The phases of each node may be determined similarly sothat the nodes are evenly spaced.

FIG. 5B is an equivalent diagram of the voltage controlled oscillator ofFIG. 5A, illustrating the plurality of inverters I1 to I6 and clocksICLK0, ICLK90, ICLK180, and ICLK270. In the example embodiment of FIGS.5A and 5B, each of nodes A and B receives two inputs (I1, I5/I2, I6) andoutputs one output (I2/I3) while each of nodes C and D receive one input(I3/I4) and outputs two outputs (I1, I4/I5, I6).

FIG. 6A illustrates a voltage controlled oscillator in accordance withan example embodiment of the present invention, which includes aplurality of inverters I1 to I8. In an example embodiment, a first loopcircuit includes inverters I1, I2, I3 and I4, a second loop circuitincludes inverters I1, I2 and I8, a third loop circuit includesinverters I3, I4 and I7, a fourth loop circuit includes inverters I2, I3and I6, a fifth loop circuit includes inverters I7 and I8, a sixth loopcircuit includes inverters I5 and I6 and a seventh loop circuit includesinverters I1, I5 and I4.

FIG. 6B is an alternative to FIG. 6A and FIG. 6C is equivalent diagramsof the voltage controlled oscillator of FIG. 6A, illustrating theplurality of inverters I1 to I8 and clocks ICLK0, ICLK90, ICLK180, andICLK270. In the example embodiment of FIGS. 6A and 6B, each of nodes A,B, C, and D receives two inputs (I1, I6/I2, I7/I3, I5/I4, I8) andoutputs one output (I2/I3/I4/I1).

FIG. 7 is a timing diagram illustrating operation of the phase lockedloop of FIG. 6A in accordance with an example embodiment of the presentinvention. As illustrated, a frequency of all internal clock signalsICLK0˜ICLK270 is two times higher than that of the external clock signalECLK. As a result, the phase locked loop of FIG. 6A may generate aplurality of internal clock signals (for example, four or more) of highfrequency (for example, 2 GHz or more) corresponding to internal clocksignals ICLK0˜ICLK270 of FIG. 1A without using dividers, even if thepower supply voltage VDD is lower (for example, less than 2V).

FIG. 8A illustrates a voltage controlled oscillator in accordance withanother example embodiment of the present invention, which includes aplurality of inverters I1 to I10. Clock signals ICLK0, ICLK72, ICLK144,ICLK216, and ICLK288 may be generated by a principle, such as phasecombination. In an example embodiment, the phases of nodes A-E maydiffer by 72°.

FIG. 8B is an example equivalent diagram of the voltage controlledoscillator of FIG. 8A, illustrating the plurality of inverters I1 to I10and Clock signals ICLK0, ICLK72, ICLK144, ICLK216, and ICLK288. In theexample embodiment of FIGS. 8A and 8B, each of nodes A-E receives twoinputs (I2, I6/I1, I10/I5, I9/I4, I7/I3, I8) and outputs two outputs(I3, I7/I2, I6/I1, I6/I5, I10/I4, I9).

FIG. 9 is a timing diagram illustrating operation of the phase lockedloop of FIG. 8A in accordance with an example embodiment of the presentinvention. As illustrated, a frequency of all five internal clocksignals ICLK0, ICLK72, ICLK144, ICLK216, and ICLK288 is twice that ofthe external clock signal ECLK. As a result, the phase locked loop ofFIG. 8A may generate a plurality of internal clock signals (for example,four or more) of high frequency (for example, 2 GHz or more) withoutusing dividers, even if the power supply voltage VDD is lower (forexample, less than 2V).

FIG. 10 is an example equivalent diagram of a voltage controlledoscillator in accordance with another example embodiment of the presentinvention, illustrating a plurality of inverters, nodes A-F, and clocksignals ICLK0, ICLK60, ICLK120, ICLK180, ICLK240, and ICLK300. In anexample embodiment, the phases of nodes A-F may differ by 60°. In theexample embodiment of FIG. 10, each of nodes A-F receives three inputsand outputs two outputs.

FIG. 11 is a timing diagram illustrating operation of the voltagecontrolled oscillator of FIG. 10 in accordance with an exampleembodiment of the present invention. Clock signals ICLK0, ICLK60,ICLK120, ICLK180, ICLK240, and ICLK300 may be generated by a principle,such as phase combination. As illustrated, a frequency of six internalclock signals ICLK0, ICLK60, ICLK120, ICLK180, ICLK240, and ICLK300 istwice that of the external clock signal ECLK. As a result, the voltagecontrolled oscillator of FIG. 10 may generate a plurality of internalclock signals (for example, four or more) of high frequency (forexample, 2 GHz or more) without using dividers, even if the power supplyvoltage VDD is lower (for example, less than 2V).

FIG. 12 is an example equivalent diagram of a voltage controlledoscillator in accordance with another example embodiment of the presentinvention, illustrating a plurality of inverters, nodes A-H, and clocksignals ICLK0, ICLK45, ICLK90, ICLK135 ICLK180, ICLK225, ICLK270, andICLK315. In an example embodiment, the phases of nodes A-F may differ by45°. In the example embodiment of FIG. 12, each of nodes A-H receivesfour inputs and outputs three outputs.

FIG. 13 is a timing diagram illustrating operation of the voltagecontrolled oscillator of FIG. 12 in accordance with an exampleembodiment of the present invention. Clock signals ICLK0, ICLK45,ICLK90, ICLK135 ICLK180, ICLK225, ICLK270, and ICLK315 may be generatedby a principle, such as phase combination. As illustrated, a frequencyof eight internal clock signals ICLK0, ICLK45, ICLK90, ICLK135 ICLK180,ICLK225, ICLK270, and ICLK315 is twice that of the external clock signalECLK. As a result, the voltage controlled oscillator of FIG. 12 maygenerate a plurality of internal clock signals (for example, four ormore) of high frequency (for example, 2 GHz or more) without usingdividers, even if the power supply voltage VDD is lower (for example,less than 2V).

As illustrated in FIGS. 4-13, a VCO, and hence a phase locked loop inaccordance with example embodiments of the present invention maygenerate n internal clock signals, where n is any integer. As describedabove, the internal clock signals may be generated by any technique, forexample, phase combination. Further, the internal clock signals may beevenly distributed, as outlined above, or unevenly distributed, ifdesired.

As set forth above, in an example embodiment of the present invention, aphase locked loop circuit may include a voltage controlled oscillatorcircuit which receive a control voltage and directly generates at leastn (where n is an integer ≧4) internal clock signals. In other exampleembodiments of the present invention, the voltage controlled oscillatorcircuit includes a hyper ring oscillator.

In other example embodiments of the present invention, the voltagecontrolled oscillator circuit generates n internal clock signals,wherein a frequency of the n internal clock signals is a multiple of afrequency of the external clock signal and wherein at least one of the ninternal clock signals is used to generate a feedback clock signal. Inother example embodiments of the present invention, the multiple isfour, eight, or 16.

In example embodiments of the present invention, the loop filter circuitis a low pass filter.

In other example embodiment of the present invention, the voltagecontrolled oscillator circuit which generates the n internal clocksignals includes n nodes and generates at least two of the n internalclock signals by phase combination.

In other example embodiments of the present invention, when n=4, twonodes of the voltage controlled oscillator circuit receives (n/2) inputsand two nodes of the voltage controlled oscillator circuit receives(n/2)−1 input. In other example embodiments of the present invention,when n is an even number greater than four, each node of the voltagecontrolled oscillator circuit receives (n/2) inputs. In other exampleembodiments of the present invention, when n is an odd number greaterthan four, each node of the voltage controlled oscillator circuitreceives (n−1)/2 inputs. In other example embodiments of the presentinvention, when n is an even number greater than four, the hyper ringoscillator includes n*((n/2) inverters. In other example embodiments ofthe present invention, when n is an odd number greater than four, thehyper ring oscillator includes n*((n−1)/2) inverters.

In example embodiment of the present invention, a phase of each of the nnodes differs by 360/n.

In an example embodiment of the present invention, when n=4, the hyperring oscillator includes four nodes, six inverters, and at least threeloop circuits or 4 nodes, eight inverters, and at least seven loopcircuits.

In another example embodiment of the present invention, when n=5, thehyper ring oscillator includes 5 nodes, ten inverters, and at leasteight loop circuits.

In another example embodiment of the present invention, when n=6, thehyper ring oscillator includes six nodes, 18 inverters, and at leasteight loop circuits.

In another example embodiment of the present invention, when n=8, thehyper ring oscillator includes 8 nodes, 32 inverters, and at least eightloop circuits.

In another example embodiment of the present invention, the controlvoltage is less than or equal to two volts, for example, 1.8 volts.

In another example embodiment of the present invention, at least one ofthe n internal clock signals is locked with the external clock signal.

In another example embodiment of the present invention, the voltagecontrolled oscillator circuit generates m*n internal clock signals(where m is an integer ≧2), a frequency of the m*n internal clocksignals is a multiple of a frequency of the external clock signal andwherein at least one of the m*n internal clock signals is used togenerate the feedback clock signal. In another example embodiment of thepresent invention, the multiple is four, eight, or 16.

In another example embodiment of the present invention, the voltagecontrolled oscillator circuit further includes a voltage controlledoscillator receiving the control voltage and generating n intermediateinternal clock signals and n dividers, dividing the n intermediateinternal clock signals into the m*n internal clock signals.

In another example embodiment of the present invention, a frequency ofthe m*n internal clock signals is a multiple of a frequency of theexternal clock signal, a frequency of the n intermediate internal clocksignals is a multiple of the frequency of the external clock signal, anda frequency of the n intermediate internal clock signals is a multipleof the frequency of the m*n internal clock signals.

In another example embodiment of the present invention, the voltagecontrolled oscillator circuit does not include a divider.

In an example embodiment of the present invention, a phase locked loopcircuit includes a voltage controlled oscillator circuit, including atleast four loops, receiving a control voltage and generating multipleinternal clock signals.

In an example embodiment of the present invention, a phase locked loopcircuit includes a voltage controlled oscillator circuit which generatesat least n (where n is an integer ≧4) internal clock signals, each froma separate loop.

FIG. 14A illustrates an example of a phase detector of FIG. 4, inaccordance with an example embodiment of the present invention. Asshown, the phase detector may include one or more flip-flops, forexample, D flip-flops, DF1 and DF2, and a NAND gate NA.

As shown, D flip-flop DF1 may receive ECLK as its clock signal, Dflip-flop DF2 may receive DCLK as its clock signal, and both D flip-flopDF1 and DF2 may receive Vcc as an input signal. An output of D flip-flopDF1 may be the UP control signal and an output of D flip-flop DF2 may bethe DN control signal. The UP and DN control signals may be NANDed byNAND gate NA and returned to D flip-flops DF1 and DF2.

The phase detector of FIG. 14A may measure a phase difference between anexternal clock ECLK and a feedback clock DCLK and may generate UP or DNcontrol signals to a charge pump (for example, charge pump (CP) 12 ofFIG. 4), in order to charge and discharge a loop filter (for example,loop filter (LF) 14 of FIG. 4). A loop filter provides a control voltage(Vc) to a VCO, in response to UP or DN control signal, as shown, forexample, in FIG. 4.

FIG. 14B illustrates an example of a phase detector 10 of FIG. 4, inaccordance with another example embodiment of the present invention. Asshown, the phase detector may include one or more flip-flops, forexample, D flip-flops, DF1 and DF2, an AND gate A, and a delay DL.

As shown, D flip-flop DF1 may receive a reference clock R as its clocksignal, D flip-flop DF2 may receive a feedback clock V as its clocksignal, and both D flip-flop DF1 and DF2 may receive Vdd as an inputsignal. An output of D flip-flop DF1 may be the UP control signal and anoutput of D flip-flop DF2 may be the DN control signal. The UP and DNcontrol signals may be ANDed by AND gate A, delayed by delay DL, andreturned to D flip-flops DF1 and DF2.

FIG. 14C is a timing diagram illustrating operation of the phasedetector of FIG. 14B in accordance with an example embodiment of thepresent invention. As shown, the phase detector measures the phaseoffset Θ_(d) between reference clock R and feedback clock V andgenerates a control signal T_(d) corresponding to the phase offset Θ_(d)for phase locking.

FIG. 15A illustrates an example of a charge pump and a loop filter, forexample, charge pump (CP) 12 and loop filter (LF) 14 of FIG. 4, inaccordance with an example embodiment of the present invention. Asshown, the charge pump (CP) 12 may include one or more transistors, forexample, P1 and N1, and the loop filter (LF) 14 may include one or morecapacitors and/or resistors, C1, C2, and R.

As shown, P1 may be connected to VCC by first current source I1 and maybe controlled by an inverse of the UP control signal UPB. N1 may beconnected to ground by second current source I2 and may be controlled bythe DN control signal. A control voltage Vc, output from the charge pump(CP) 12, may be supplied to C1 and R/C2 in parallel. As shown, R and C2may be arranged in series.

In example operation, as shown, for example, in FIG. 15B, if a referenceclock signal (RCLK) leads a feedback clock signal (VCLK) from a VCO (forexample, any of the VCOs shown in FIGS. 1A, 1B, 2, 4, 5A, 6A, 8A, 10, or12 above), an UP control signal may be output to the charge pump (CP)12. The charge pump (CP) 12 may charge the loop filter (LF) 14 so that avoltage level of the control voltage Vc is increased (for example,gradually) until a locking operation is completed in the phase lockedloop. In an example embodiment, the loop filter 14 is a low pass filter.

In example operation, as shown, for example, in FIG. 15C, if thereference clock signal (RCLK) lags the feedback clock signal (VCLK) ofVCO, a DN control signal may be output to the charge pump (CP) 12. Thecharge pump (CP) 12 may charge the loop filter (LF) 14 so that a voltagelevel of the control voltage Vc is decreased (for example, gradually)until a locking operation is completed in the phase locked loop.

FIGS. 16A and 16B illustrate examples of a divider for example, divider20 of FIG. 4, in accordance with an example embodiment of the presentinvention. As shown, the divider may include one or more one or moreflip-flops, for example, D flip-flops, DF3, DF4, and/or DF5.

As shown in FIG. 16A, D flip-flop DF3 may receive one or more internalclock signals iclk (for example, any one of internal clocks ICLK0˜ICLKnof FIG. 4) as its clock signal, its own output QB as an input signal,and output clock signal oclk as a feedback clock signal (for example,feedback clock signal DCLK of FIG. 4). In the example embodiment of FIG.16A, the divider is a “divide by 2” divider. For example, if theinternal clock signal iclk has a frequency of 2 GHz, the output clocksignal oclk has a frequency of 1 GHz.

As shown in FIG. 16B, D flip-flops DF4 and D5 may be arranged in series.D flip-flop DF4 may receive one or more internal clock signals iclk (forexample, any one of internal clocks ICLK0˜ICLKn of FIG. 4) as its clocksignal, its own output QB as an input signal, and output clock signaliclk′ as an output clock signal. Similarly, D flip-flop DF5 may receivethe clock signal iclk′ as its clock signal, its own output QB as aninput signal, and output clock signal oclk as a feedback clock signal(for example, feedback clock signal DCLK of FIG. 4). In the exampleembodiment of FIG. 16B, the divider is a “divide by 4” divider. Forexample, if the internal clock signal iclk has a frequency of 4 GHz, theclock signal iclk′ has a frequency of 2 GHz, and the output clock signaloclk has a frequency of 1 GHz.

FIG. 17 illustrates a phase locked loop in accordance with anotherexample embodiment of the present invention, which may include a phasefrequency detector (PFD) 10, a charge pump (CP) 12, a loop filter (LF)14, a voltage controlled oscillator (VCO) 16′, one or more dividers18-1′, 18-2′, and/or one or more dividers 20. The VCO 16′ may directlygenerate a plurality of even higher frequency internal clock signals(for example, 4 GHz or more) corresponding to internal clock signalsICLK0˜ICLK270 of FIG. 1A, with relatively few dividers, and even thougha power supply voltage VDD is relatively low (for example, less than2V). In an example embodiment, the one or more dividers 18-1′, 18-2′ maygenerate a plurality of higher frequency internal clock signals ICLK1,ICLK1B, ICLK2, ICLK2B, . . . , ICLKn, ICLKnB (for example, 2 GHz ormore) even though a power supply voltage VDD is relatively low (forexample, less than 2V).

In an example embodiment, the VCO 16′ may be implemented with hyper ringoscillator, which may directly generate a plurality of internal clocksignals (for example, four clock signals or more) which have a regularphase difference.

It is noted that each of the alternatives and variations discussed abovewith respect to the phase locked loops of FIGS. 4-13, are alsoapplicable to the phase locked loop of FIG. 17.

Although example embodiments of the present invention have beenillustrated in the context of an analog phase locked loop, as shown forexample, in FIGS. 4 and 17, one or more concepts of the presentinvention may also be applied to digital phase locked loop, as shown inFIG. 18. FIG. 18 illustrates a phase locked loop in accordance withanother example embodiment of the present invention, which may include aphase frequency detector (PFD) 10, a counter 32, a digital-to-analogconverter (DA) 34, a loop filter (LF) 36, a voltage controlledoscillator (VCO) 38, and/or one or more dividers 40.

The VCO 38 may directly generate a plurality of higher frequencyinternal clock signals (for example, 2 GHz or more) corresponding tointernal clock signals ICLK0˜ICLK270 of FIG. 1A even though a powersupply voltage VDD is relatively low (for example, less than 2V). In anexample embodiment, the VCO 38 may be implemented with a hyper ringoscillator, which may generate directly a plurality of internal clocksignals (for example, four clock signals or more) which have a regularphase difference. In addition, a VCO in accordance with an exampleembodiment of the present invention. for example VCO 38, may have areduced chip area because dividers, for example, dividers 18-1, 18-2,are not needed.

As shown, the counter 32 may be controlled to conduct up or downcounting in response to UP or DN control signal so that the value of acounting output signal (CNT) composed of a plurality of bits isincreased or decreased. For example, “1110..000” may be increased to“1111..000” upon receipt of the UP signal or “1110..000” may bedecreased to “1100-000” upon receipt of the DN signal.

FIG. 19 illustrates an example of a digital-to-analog converter and aloop filter, for example, digital-to-analog converter (DA) 34, a loopfilter (LF) 36 of FIG. 18, in accordance with an example embodiment ofthe present invention. As shown, the digital-to-analog converter (DA) 34may include a first circuit CM including one or more transistors, forexample, P2 and P3, a second circuit CC including one or moretransistors, for example, N3-1, . . . N3-i (where i is the number ofbits in the counting output signal (CNT)), and one or more transistors,for example, bias transistor N2.

As shown and described above with respect to FIG. 15 and loop filter(LF) 14, loop filter (LF) 36 may include one or more capacitors and/orresistors, C1, C2, and R. A control voltage Vc, output from thedigital-to-analog converter (DA) 34, may be supplied to C1 and R/C2 inparallel. As shown, R and C2 may be arranged in series.

The value of Vbias supplied to N2 maintains a desired voltage (forexample, one half VCC).

In operation, if a value of the counting output signal (CNT) composed ofa plurality of bits is all high (111..11), all transistors (N3-1˜N3-i)may be turned on so that a voltage of node a is at its lowest level. Inthis state, a control voltage Vc is increased to its highest level.

Conversely, if the value of CNT is composed of 1000..00, all transistors(N3-2˜N3-i) except N3-1 may be turned off so that the value of node a isat its highest level. In this state, the control voltage Vc is decreasedto its lowest level. As shown above, the value of Vc may be adjusted bythe counting output signal CNT.

It is noted that each of the alternatives and variations discussed abovewith respect to the analog phase locked loops of FIGS. 4-17, are alsoapplicable, to the extent feasible, to the digital phase locked loop ofFIG. 18.

FIG. 20 illustrates a simulation of frequency variation (C) of a voltagecontrolled oscillator in accordance with an example embodiment of thepresent invention compared to frequency variation (P) of a conventionalvoltage controlled oscillator. As shown in FIG. 20, 2 GHz internalclocks (for example, ICLK0, ICLK90, ICLK180, ICLK270 of FIG. 4) may bedirectly generated from a VCO in accordance with an example embodimentof the present invention when a control voltage Vc is 1.43V. However, inorder to generate 2 GHz internal clocks in a conventional PLL, aconventional VCO must output 4 GHz clock signals (for example CLK, CLKBof FIG. 1A), which requires a control voltage Vc of well over 1.8V.Therefore, it is difficult to output higher frequency internal clocksignals in a low power semiconductor device (under 1.8V), using aconventional PLL with a conventional VCO.

FIG. 21 illustrates an example of a memory system and FIG. 22illustrates an example of a memory device, for example the memory device200-1 of FIG. 21, including associated control logic, in accordance withan example embodiment of the present invention. More particularly, thememory module 200 of FIGS. 21 and 22 may include one or more of thephase locked loops described above in conjunction with FIGS. 4-19 asphase locked loop 24.

As shown, a memory system in accordance with an example embodiment ofthe present invention may include a memory controller 100 and a memorymodule 200. The memory module 200 may further include a plurality ofmemory devices 200-1, 200-2, 200-x, which may be implemented, forexample, by DRAMs.

The memory controller 100 may output an external clock signal ECLK, oneor more command signals COM, one or more address signals ADD, and/or oneor more data signals DATA to the memory module 200.

The memory module 200 may also output one or more data signals DATA tothe memory controller 100. In the example shown in FIG. 21, the one ormore data signals DATA may be composed of a serial stream of 2^(n) bits,represented by [1:2^(n)] DATA11 to [1:2^(n)] DATAxj. As shown in FIG.21, memory device 200-1 may receive the external clock signal ECLK, theone or more command signals COM, the one or more address signals ADD,and the DATA signals DATA 11 to DATA 1 j. Similarly, memory device 200-2may receive the external clock signal ECLK, the one or more commandsignals COM, the one or more external address signals ADD, and the DATAsignals DATA 21 to DATA 2 j, and memory device 200-x may receive theexternal clock signal ECLK, the one or more command signals COM, the oneor more address signals ADD, and the DATA signals DATA x1 to DATA xj.

As shown, in the example memory system of FIG. 21, each memory device200-1, 200-2, 200-x may receive or output DATA composed of serial 2^(n)bits during one clock cycle of the external clock signal ECLK. Inaddition, DATA of j bits may be written or read at the same time.

As shown in FIG. 22, the associated control logic may include an addressbuffer (ADD BUF) 10, a command decoder (COM DEC) 12, one or moreserial-to-parallel converters 14-1 to 14-j (j corresponding to the j inFIG. 1A), one or more parallel-to-serial converters 16-1 to 16-j, thememory cell array 18, a row decoder 20, a column decoder 22, a PLL 24,and/or a control signal generation circuit (CSG Ckt.) 26The addressbuffer (ADD BUF) 10 may receive one or more external input addresses(ADD) to generate a row address (RA), supplied to the row decoder 20, inresponse to an active command signal (ACT).

The row decoder 20 may activate a main word line enable signal (MWE)corresponding to a plurality of row addresses generated from a pluralityof row address buffers so that a desired word line (not shown) may beselected in the memory cell array 18. The address buffer (ADD BUF) 10may also generate a column address (CA), supplied to the column decoder22, in response to a read command (RE) or a write command (WE) decodedfrom the one or more command signals COM.

The column decoder 22 may receive a plurality of column addresses toactivate a corresponding column select line (CSL). A plurality of bitlines of the memory cell array 18 may be selected in response to theselected CSL so that a plurality of data may be written to or read fromthe selected memory cells.

As set forth above, the command decoder 12 may generate an activecommand, a read command and a write command after receiving a pluralityof external command signals (COM), for example, RASB, CASB, WEB etc.

Each serial-to-parallel converter (14-1 to 14-j) may receive serial dataDATA composed of 2^(n) bit data and output 2^(n) bit parallel datathrough 2^(n) data bus lines simultaneously to the memory cell array 18,in response to a write command signal (WE) and a plurality of controlsignals (P1˜P(2^(n))). If the number of data input/data output pins (DQ)is j, the number of serial-to-parallel converter is also j. In addition,each of the serial-to-parallel converters (14-1 to 14-j) may be coupledto the memory cell array 18 via 2^(n) data bus lines.

Each parallel-to-serial converter (16-1 to 16-j) may receive 2^(n) bitdata from a memory cell array 18 in parallel and output 2^(n) bit serialdata responsive to a read command signal (RE) and the plurality ofcontrol signals (P1˜P(2^(n))). If the number of data input/data outputpins (DQ) is j, the number of parallel-to-serial converters is also j.

The phase lock loop 24 may receive the external clock signal ECLK andperform a locking operation to output an internal clock signal CLK1,which is locked with ECLK. After completing the locking operation, thephase lock loop 24 may output a plurality of internal clock signals(CLK1˜CLKI) to the control signal generation circuit (CSG Ckt.) 26. Thecontrol signal generation circuit (CSG Ckt.) 26 may generate theplurality of control signals (P1˜P(2^(n))).

It will be apparent to those skilled in the art that other changes andmodifications may be made in the above-described example embodimentswithout departing from the scope of the invention herein, and it isintended that all matter contained in the above description shall beinterpreted in an illustrative and not a limiting sense.

1. A phase locked loop circuit, comprising: a phase detector receivingan external clock signal and a feedback clock signal and outputting anup signal when a phase of the external clock signal leads a phase of thefeedback clock signal and outputting a down signal when the phase of theexternal clock signal lags the phase of the feedback clock signal; aloop filter circuit increasing a control voltage in response to the upsignal and decreasing the control voltage in response to the downsignal; and a voltage controlled oscillator circuit receiving thecontrol voltage and directly generating at least n (where n is aninteger ≧4) internal clock signals, wherein the voltage controlledoscillator circuit includes a hyper-ring oscillator, a frequency of then internal clock signals is a multiple of a frequency of the externalclock signal without using a divider and the n internal clock signalshave different phases from one another and have the same phasedifference and at least one of the n internal clock signals is used togenerate the feedback clock signal and the feedback clock signal islocked with the external clock signal, and wherein the hyper-ringoscillator comprises at least two loops connecting inverting circuits asa ring-type, at least one of the inverting circuits is commonlyconnected to the at least two loops, and at least one of the n internalclock signals is generated by combining phases of output signals of atleast two of the inverting circuits.
 2. The phase locked loop circuit ofclaim 1, further comprising: a divider, dividing a frequency of the atleast one of the n internal clock signals to generate the feedback clocksignal.
 3. The phase locked loop circuit of claim 2, the dividerincluding at least one D flip-flop.
 4. The phase locked loop circuit ofclaim 1, wherein the loop filter circuit is an analog loop filtercircuit.
 5. The phase locked loop circuit of claim 4, wherein the loopfilter circuit includes a charge pump and a low pass-filter, the chargepump charging or discharging the low pass filter to control a level ofthe control voltage until a locking operation is completed in the phaselocked loop circuit.
 6. The phase locked loop circuit of claim 1,wherein the voltage controlled oscillator circuit generates outputsignals of the inverting circuits as the n internal clock signals. 7.The phase locked loop circuit of claim 6, wherein when n=4, two of theinverting circuits receive (n/2) inputs and the other two of theinverting circuits receive (n/2)−1 input.
 8. The phase locked loopcircuit of claim 6, wherein when n is an even number greater than four,each of the inverting circuits receives (n/2) inputs.
 9. The phaselocked loop circuit of claim 6, wherein when n is an odd number greaterthan four, each of the inverting circuits receives (n−1)/2 inputs. 10.The phase locked loop circuit of claim 6, wherein when n is an evennumber greater than four, the inverting circuits are n*(n/2) inverters.11. The phase locked loop circuit of claim 6, wherein when n is an oddnumber greater than four, the inverting circuits are n*((n−1)/2)inverters.
 12. The phase locked loop circuit of claim 6, wherein a phaseof each of the n internal clock signals differs by 360/n.
 13. The phaselocked loop circuit of claim 8, wherein when n=4, the inverting circuitsinclude four nodes, six inverters, and at least three loop circuits. 14.The phase locked loop circuit of claim 8, wherein when n=4, theinverting circuits include 4 nodes, eight inverters, and at least sevenloop circuits.
 15. The phase locked loop circuit of claim 8, whereinwhen n=5, the inverting circuits include 5 nodes, ten inverters, and atleast eight loop circuits.
 16. The phase locked loop circuit of claim 8,wherein when n=6, the inverting circuits include six nodes, 18inverters, and at least eight loop circuits.
 17. The phase locked loopcircuit of claim 8, wherein when n=8, the inverting circuits include 8nodes, 32 inverters, and at least eight loop circuits.
 18. The phaselocked loop circuit of claim 1, wherein the voltage controlledoscillator circuit generates m*n internal clock signals (where m is aninteger ≧2), a frequency of the m*n internal clock signals is a multipleof a frequency of the external clock signal and wherein at least one ofthe m*n internal clock signals is used to generate the feedback clocksignal.
 19. The phase locked loop circuit of claim 18, the voltagecontrolled oscillator circuit further including: a voltage controlledoscillator receiving the control voltage and generating n intermediateinternal clock signals, and n dividers, dividing the n intermediateinternal clock signals into the m*n internal clock signals.
 20. Thephase locked loop circuit of claim 19, wherein a frequency of the m*ninternal clock signals is a multiple of a frequency of the externalclock signal, a frequency of the n intermediate internal clock signalsis a multiple of the frequency of the external clock signal, and afrequency of the n intermediate internal clock signals is a multiple ofthe frequency of the m*n internal clock signals.
 21. A phase locked loopcircuit, comprising: a phase detector receiving an external clock signaland a feedback clock signal and outputting an up signal when a phase ofthe external clock signal leads a phase of the feedback clock signal andoutputting a down signal when the phase of the external clock signallags the phase of the feedback clock signal; a loop filter circuitincreasing a control voltage in response to the up signal and decreasingthe control voltage in response to the down signal, and including acounter, a digital-to-analog converter and a loop filter, the countercounting up in response to the up signal and counting down in responseto the down signal to control a level of the control voltage until alocking operation is completed in the phase locked loop circuit; and avoltage controlled oscillator circuit receiving the control voltage anddirectly generating at least n (where n is an integer ≧4) internal clocksignals, wherein the voltage controlled oscillator circuit includes ahyper-ring oscillator, a frequency of the n internal clock signals is amultiple of a frequency of the external clock signal without using adivider, the internal clock signals have different phases from oneanother and have the same phase difference, at least one of the ninternal clock signals is used to generate the feedback clock signal andthe feedback clock signal is locked with the external clock signal, andwherein the hyper-ring oscillator comprises at least two loopsconnecting inverting circuits as a ring-type, at least one of theinverting circuits is commonly connected to the at least two loops, andat least one of the n internal clock signals is generated by combiningphases of output signals of at least two of the inverting circuits. 22.The phase locked loop circuit of claim 21, wherein the voltagecontrolled oscillator circuit generates m*n internal clock signals(where m is an integer ≧2), a frequency of the m*n internal clocksignals is a multiple of a frequency of the external clock signal andwherein at least one of the m*n internal clock signals is used togenerate the feedback clock signal.
 23. The phase locked loop circuit ofclaim 22, the voltage controlled oscillator circuit further including: avoltage controlled oscillator receiving the control voltage andgenerating n intermediate internal clock signals, and n dividers,dividing the n intermediate internal clock signals into the m*n internalclock signals.
 24. The phase locked loop circuit of claim 23, wherein afrequency of the m*n internal clock signals is a multiple of a frequencyof the external clock signal, a frequency of the n intermediate internalclock signals is a multiple of the frequency of the external clocksignal, and a frequency of the n intermediate internal clock signals isa multiple of the frequency of the m*n internal clock signals.
 25. Thephase locked loop circuit of claim 1, wherein the voltage controlledoscillator circuit does not include a divider.
 26. A method of lockingthe phase of a feedback clock signal to an external clock signal,comprising: receiving the external clock signal and the feedback clocksignal; outputting an up signal when a phase of the external clocksignal leads a phase of the feedback clock signal and outputting a downsignal when the phase of the external clock signal lags the phase of thefeedback clock signal; increasing a control voltage in response to theup signal and decreasing the control voltage in response to the downsignal; and directly generating at least n (where n is an integer ≧4)internal clock signals; and generating the feedback clock signal from atleast one of the n internal clock signals, wherein a frequency of the ninternal clock signals is a multiple of a frequency of the externalclock signal without using a divider and the internal clock signals havedifferent phases from one another and have the same phase difference, atleast one of the n internal clock signals is used to generate thefeedback clock signal and the feedback clock signal is locked with theexternal clock signal, and wherein the n internal clock signals aregenerated by using the hyper-ring oscillator comprising at least twoloops connecting inverting circuits as a ring-type, at least one of theinverting circuits is commonly connected to the at least two loops, andat least one of the n internal clock signals is generated by combiningphases of output signals of at least two of the inverting circuits. 27.A phase locked loop circuit, comprising: a phase detector receiving anexternal clock signal and a feedback clock signal and outputting an upsignal when a phase of the external clock signal leads a phase of thefeedback clock signal and outputting a down signal when the phase of theexternal clock signal lags the phase of the feedback clock signal; aloop filter circuit increasing a control voltage in response to the upsignal and decreasing the control voltage in response to the downsignal; and a voltage controlled oscillator circuit, including at leastfour loops, receiving the control voltage and generating multipleinternal clock signals, wherein the voltage controlled oscillatorcircuit includes a hyper-ring oscillator, a frequency of the multipleinternal clock signals is a multiple of a frequency of the externalclock signal without using a divider, the multiple clock signals havedifferent phases from one another and have the same phase difference, atleast one of the multiple internal clock signals is used to generate thefeedback clock signal and the feedback clock signal is locked with theexternal clock signal, and wherein the four loops are connectedinverting circuits as a ring-type, at least one of the multipleinverting circuits is commonly connected to the at least two loops, andat least one of the multiple internal clock signals is generated bycombining phases of output signals of at least two of the invertingcircuits.